By Mostafa Abd-El-Barr, Hesham El-Rewini
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Extra resources for Advanced Computer Architecture and Parallel Processing
In equal priority, when two or more requests are made, there is equal chance of any one request being processed. In the LRU algorithm, the highest priority is given to the processor that has not used the bus for the longest time. 3 SWITCH-BASED INTERCONNECTION NETWORKS In this type of network, connections among processors and memory modules are made using simple switches. Three basic interconnection topologies exist: crossbar, single-stage, and multistage. 1 Crossbar Networks A crossbar network represents the other extreme to the limited single bus network.
2 Example single bus system. TEAM LinG - Live, Informative, Non-cost and Genuine ! 2 BUS-BASED DYNAMIC INTERCONNECTION NETWORKS 21 shared bus. The use of local caches reduces the processor – memory trafﬁc. All processors communicate with a single shared memory. The typical size of such a system varies between 2 and 50 processors. The actual size is determined by the trafﬁc per processor and the bus bandwidth (deﬁned as the maximum rate at which the bus can propagate data once transmission has started).
Ignore the communication time. (c) A MIMD computer system having 64 independent elements accessing a shared memory through an interconnection network. Ignore the communication time. (d) Repeat (b) and (c) above if the communication time takes two time units. 10. Conduct a comparative study between the following interconnection networks in their cost, performance, and fault tolerance: (a) bus; (b) hypercube; (c) mesh; (d) fully connected; (e) multistage dynamic network; (f) crossbar switch. REFERENCES Abraham, S.
Advanced Computer Architecture and Parallel Processing by Mostafa Abd-El-Barr, Hesham El-Rewini